Steep subthreshold slope nanoelectromechanical field-effect transistors with nanowire channel and back gate geometry

Significant physical challenges remain for CMOS technology to increase I on and decrease I off as transistor dimension and power supply voltages continue downscaling. For I off , a physical barrier exists as exhibited in the subthreshold slope SS = |(∂V g )/(∂lnI d )| = ln10·k B T/q, which is limited to > 60 mV/dec at room temperature due to electron thermal distribution. To circumvent this fundamental thermodynamical limit, we have designed the first integration of semiconductor nanowires (NWs) and nanoelectromechanical system (NEMS) field effect transistor structure (NW-NEMFET). We have previously demonstrated 0.5 ps intrinsic delay and near ballistic operation in quantum confined semiconductor heterostructure NWFETs with diameters less than 15 nm.[1] The current design uses high performance suspended semiconductor NWs as the conduction channel, while the electrostatic pull-in of the NW towards the gate stack enables abrupt switching to the off-state leading to high frequency, low power nanoelectronics. We show that compared to planar suspended-gate FET (SGFET) design [2], NW-NEMFET allows zero SS with 10 15 on-off ratio and near 1 V pull-in voltage (V pi ) due to enhanced 3D capacitive coupling, as well as operation at very-high-frequency (VHF) and even ultra-high-frequency (UHF) due to the NW beams' extremely high aspect ratio and small dimensions. [3] Fabrication and characterization of will be discussed.