A Low-Power Reversible Full-Adder Using Novel 3X3 Reversible Gate

Reversible computation has become an alluring concept in low power circuit design. The conventional computations generate more heat due to the effect of logic gates which are irreversible in nature. For low power consumption circuit must be designed with reversible logic gates that have both forward and backward deterministic. The main focus of this study involves two primary design implementations. The earlier presents the design of Modified Toffoli Reversible gate (MTGDI) gate. The proposed MTGDI gate is fully reversible and designed with Gate diffusion input (GDI) logic design technique which consumes less power and less area. The last presents the realization of full adder by incorporating the proposed MTGDI gate. The performance of the proposed study have been compared with its counterpart in terms of transistor count, quantum cost, PDP and garbage output. From this study it is tacit that the proposed model produces maximum of 47.3% of PDP improvement with 7% of delay and 28.5% of quantum cost improvement.