A 10-bit 2MS/s SAR ADC Using a Dynamic Element Matching Technique

Abstract—A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) using metal layer parasitic capacitance is presented. A data-weighted averaging (DWA) technique is adopted to attenuate the nonlinearity caused by the capacitor mismatch. A monotonic capacitor switching procedure is used to reduce the average switching energy and total capacitance. The proposed ADC fabricated in a 0.13μm CMOS process achieves a peak signal-to-noise and distortion ratio (SNDR) of 56.5 dB and a spurious free dynamic range (SFDR) of 65.1 dB with 2 MHz sampling frequency while consuming 3.12mW at a 1.2 V supply voltage.