Topography impacts on line-width control for gate level lithography

The dimensional variations caused by topography differences between active and non active shallow trench isolation (STI) areas, at the gate level, need to be controlled through proper use of reflectivity control methods. Line-width variation caused by topography can either be a disastrous problem or so small that it is hard to detect. Some of the primary variables include the step-height, active-area-width and planarization length of the BARC being used. In order to experimentally compare different reflectivity control methods, wafers were built with steps ranging from 7.5 nm higher to 27 nm lower than the surroundings. Organic BARC thicknesses of 90 and 130 nm were evaluated. Two resist thicknesses were also evaluated. Along with examining the effect of step-height, we also examined the effect of active-area-widths ranging from 0.5 um to 4.5 um. The data demonstrate that line-width variation going over this variety of steps is well under 1 nm when BARC and resist thicknesses are optimized.