Pulse processing circuit and the frequency multiplier circuit

Are serially connected PMOS transistors (P1 ~ Pn) between the power source terminal (VD) and the output terminal (the OUTB) and a PMOS transistor (P1 '~ Pn'), between the output terminal (the OUTB) and a ground terminal (G), respectively the gate of the NMOS transistor are connected in series (N1 ~ Nn) and NMOS transistor (N1 '~ Nn'), input terminals (S1 ~ Sn) are connected to the PMOS transistor (P1 '~ Pn') and the NMOS transistors (N1 ~ Nn) of respectively, while the inverter (IV1 ~ IVn), are connected to the gate of the PMOS transistor (P1 ~ Pn) and the NMOS transistor (N1 '~ Nn') of. Thus, even when increasing the number of inputs may be low voltage, suppressing increase in power consumption.