Mandrel-based patterning: density multiplication techniques for 15nm nodes

In many ways, sidewall spacer double patterning has created a new paradigm for lithographic roadmaps. Instead of using lithography as the principal process for generating device features, the role of lithography becomes to generate a mandrel (a pre-pattern) off-of-which one will subsequently replicate patterns with various degrees of density multiplication. Under this new paradigm, the innovativeness of various density multiplication techniques is as critical to the scaling roadmap as the exposure tools themselves. Sidewall spacer double patterning was the first incarnation of mandrel based patterning; adopted quickly in NAND flash where layouts were simple and design space was focused. But today, the use of advanced automated decomposition tools are showing spacer based patterning solutions for very complex logic designs. Future incarnations can involve the use of laminated spacers to create quadruple patterning or by retaining the original mandrel as a method to obtain triple patterning. Directed self-assembly is yet another emerging embodiment of mandrel based patterning, where selfseparating polymers are registered and guided by the physical constraint of a mandrel or by chemical pre-pattern trails formed onto the substrate. In this summary of several bodies of work, we will review several wafer level demonstrations, all of which use various forms of mandrel or stencil based density multiplication including sidewall spacer based double, triple and quadruple patterning techniques for lines, SADP for via multiplication, and some directed self-assembly results all capable of addressing 15nm technology node requirements and below. To address concerns surrounding spacer double patterning design restrictions, we show collaboration results with an EDA partner to demonstrate SADP capability for BEOL routing layers. To show the ultimate realization of SADP, we partner with IMEC on multiple demonstrations of EUV+SADP.