Efficient Buffer Design and Implementation for Wormhole Routers on FPGAs

Several studies show that the overall network performance in worhmole routers is degraded due to congestion at a specific part in the network while other parts have little or no flow of data. Our design improves the performance of the wormhole router by adding a central channel that is shared among the physical channels. Experimental results using the uniform random traffic and the hotspot traffic show that enabling the central buffer increases the performance of the network by as much as 13%. On the implementation side, buffers consume more than half of the router’s area and power, and the coarse-grain nature of embedded BRAMs in most FPGAs has led to very inefficient utilization of such memory resources. We propose two different types of buffer sharing: 1. Sharing between the processors of a system on chip and router buffers; 2. Sharing BRAMs among different virtual and physical channels inside the wormhole router. Our designs target the Xilinx Virtex-6 FPGAs and the results show a decrease of 87.5% in BRAM usage on the expense of a slight register increase. Our techniques can be easily applied to any other FPGA-based buffer implementation.