Design of Adjacent Interconnect Processor Based on RISC-V

In this paper, based on RISC-V architecture, the processor design of a reconfigurable array with adjacency interconnect is realized by adding adjacency interconnect instructions and related circuits, using the classical five-stage pipeline structure. In addition, this processor also realizes the basic instruction set of RV32I, ALU also has a two-level pipelining multiplier, can realize multiplication operation. The proposed processor is implemented in Verilog HDL and further prototyped on FPGA development board, BASYS 3. The processor operates at a frequency of 100 MHz and the Slice LUTS and Slice Registers are occupying 3816 and 2131, respectively.