Coherency of i/o channel controller of data processing system and synchronizing device and method

PROBLEM TO BE SOLVED: To obtain a more efficient IOCC design by not applying any I/O bus controller(IOBC) to a data cache and cache controller, but an I/O channel controller(IOCC) related to a system bus controller in the IOCC. SOLUTION: A system bus 108 and I/O bus 220 are connected to an IOCC 114 A system bus controller(SBC) 202 does not control any IOBC 201, but control a cache controller 203. Consequently, the SBC 202 offers the access to a DMA readout data cache or DMA write through data cache to the IOBC 201 at all times. Therefore, the SBC 202 can effectively execute system bus transfer. Because of the structure of the IOCC 114, system bus 108 searching operation generates an address particle size and the asynchronous handshake between the SBC 202 and IOBC 210 becomes the minimum. COPYRIGHT: (C)1996,JPO