Low power implementation of FSM based vending machine on FPGA

The central idea of this work is to design a vending machine that will be able to provide a number of items like soft drink, cake & coldrinks to people. The machine will also deliver the change, depending on the amount of money inserted and the price of product. At the same time we have made efforts to make the design of the Vending Machine power efficient by using power reduction techniques. In this process we have tested our design at different frequencies and analyzed the consumed power. Next, we have also calculated the power at different frequencies with different IO STANDARD like LVCMOS33, LVCMOS12, SSTL18_I, HSTL_I_18. The proposed design is tested and implemented using VERILOG HDL and XILINX ISE 14.2 targeting XC3S500E FPGA. The result shows optimization of power.