for Pipelined System Design

We present GRTL, a graphical dcsign tool spccifically for manual design of synchronous pipclincs at the rcgistcr lransfcr level. Abctractiona (paramcterizcd bchavioral cornponcnts, abstract signals) and AI methodology simplify input and reduce detail, yet useful timing analyses can bc obtaincd. Features include integrated interactive dcsign blackboard. Werner diagram and clocking formalisms for dcsign corrcct- ness, open library, reversible functional simulator, and down- loading facility for external silicon compilation. Earlicr work is contrasted.