Model based OPC for implant layer patterning considering wafer topography proximity (W3D) effects
2012
Implant layer patterning is becoming challenging with node shrink due to decreasing critical dimension (CD) and usage
of non-uniform reflective substrates without bottom anti-reflection coating (BARC).
Conventional OPC models are calibrated on a uniform silicon substrate and the model does not consider any wafer
topography proximity effects from sub-layers. So the existing planar OPC model cannot predict the sub-layer effects
such as reflection and scattering of light from substrate and non-uniform interfaces. This is insufficient for layers without
BARC, e.g., implant layer, as technology node shrinks.
For 45-nm and larger nodes, the wafer topography proximity effects in implant layer have been ignored or compensated
using rule based OPC. When the node reached 40 nm and below, the sub-layer effects cause undesired CD variation and
resist profile change. Hence, it is necessary to model the wafer topography proximity effects accurately and compensate
them by model based OPC. Rigorous models can calculate the wafer topography proximity effects quite accurately if
well calibrated. However, the run time for model calibration and OPC compensation are long by rigorous models and
they are not suitable for full chip applications. In this paper, we demonstrate an accurate and rapid method that considers
wafer topography proximity effects using a kernel based model. We also demonstrate application of this model for full
chip OPC on implant layers.
Keywords:
- Correction
- Source
- Cite
- Save
- Machine Reading By IdeaReader
0
References
6
Citations
NaN
KQI