EUV and optical lithographic pattern shift at the 5nm node

At the 5 nm technology node there are competing strategies for patterning: high-NA EUV, double patterning 0.33 NA EUV and a combination of optical self-aligned solutions with EUV. This paper investigates the impact of pattern shift based on the selected patterning strategy. A logic standard cell connection between TS and M0 is simulated to determine the impact of lithographic pattern shift on the overlay budget. At 5 nm node dimensions, high-NA EUV is necessary to expose the most critical layers with a single lithography exposure. The impact of high-NA EUV lithography is illustrated by comparing the pattern shift resulting from 0.33 NA vs. 0.5x NA. For the example 5 nm transistor, cost-beneficial lithography layers are patterned with EUV and the other layers are patterned optically. Both EUV and optical lithography simulations are performed to determine the maximum net pattern shift. Here, lithographic pattern shift is quantified in terms of through-focus error as well as pattern-placement error. The overlay error associated with a hybrid optical/self-aligned and EUV cut patterning scheme is compared with the results of an all EUV solution, providing an assessment of two potential patterning solutions and their impact the overall overlay budget.