A 100 MHz macropipelined CISC CMOS microprocessor

Roy Badeau,Ruth I. Bahar,Debra Bernstein,Larry L. Biro,William J. Bowhill,John F. Brown,Michael A. Case,Ruben W. Castelino,Elizabeth M. Cooper,M. A. Delaney,D.R. Deverell,John H. Edmondson,J. J. Ellis,Timothy C. Fischer,T.F. Fox,Michael K. Gowan,P.E. Gronowski,W.V. Herrick,A. Jain,Jeanne E. Meyer,D.G. Miner,Hamid Partovi,V. Peng,Ronald P. Preston,Chandrasekhara Somanathan,Rebecca L. Stamm,Stephen C. Thierauf,M. Uhler,Nicholas D. Wade,William R. Wheeler

A 100 MHz macropipelined CISC CMOS microprocessor

1992

A macropipelined CISC microprocessor implemented in a 0.75- mu m CMOS 3.3-V three-metal-layer technology is described. The 1.3 M-transistor custom chip measures 1.62*1.46 cm/sup 2/, dissipates 18 W (peak), and is packaged in a 339-pin PGA. The chip implements a macroinstruction pipeline to execute the instruction set of a popular CISC minicomputer. A block diagram of the major functional units is shown along with die micrograph. >

Keywords:

Electronic engineering
Chip
Embedded system
CMOS
Computer hardware
Microprocessor
Computer science
Complex instruction set computing
Minicomputer
Instruction set
Block diagram

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