Materials, processing and reliability of low temperature bonding in 3D chip stacking

Abstract Due to the advantages of small form factor, high performance, low power consumption, and high density integration, three-dimensional integrated circuits (3D ICs) have been generally acknowledged as the next generation semiconductor technology. Low temperature bonding is the key technology to ensure the chip (or wafer) stacking in 3D ICs. In this paper, different low temperature bonding methods for chip (or wafer) stacking were reviewed and described systematically. Materials, processing and reliability will be extremely important, their effects on the 3D IC structure were addressed in detail, the challenging reliability issues may be considered as the major concern in the future work. The latest development of low temperature bonding in 3D ICs is also given here, which helpful may provide a reference for the further study of low temperature bonding.