Suppression technique of vertical leakage current in GaN-on-Si power transistors

This paper analyzes the possible physical mechanisms responsible of high vertical leakage in GaN-on-Si power transistors. Vertical leakage and back bias measurement are presented and compared against TCAD simulations with the aim of identifying the physical phenomena and parameters that impact the vertical leakage. An easy-to-implement TCAD approach for simulating the non-ideality of the AlN nucleation layer and AlN/Si interface is introduced. Finally, a method to largely suppress the vertical leakage via implantation of highly doped p++ wells at the AlN/Si interface is proposed and investigated via TCAD simulations. The suggested technique allows for a reduction of five orders of magnitude in the leakage current when a p++ surface doping in excess of 5 × 1019 cm−3 is implanted at the Si-substrate surface. In this work, a normally-on HEMT is investigated but the analysis can be extended to any GaN-on-Si power device.