Advances of Chip-Scale Atomic Clock in Peking University in 2020

Chip-scale atomic clock (CSAC) has the advantages of small volume, low power consumption and high frequency stability. We made improvements to the physics package and control algorithm of our CSAC in the last year, which reduces the power consumption of PP and improves the frequency stability of CSAC. Meanwhile, the 1 pulse per second (1PPS) time error of CSAC is also minimized. The total power consumption of PP is about 80 mW, and 1PPS time error keeps less than 20 ns in 3 minutes.