Statistical DRAM modeling

Cycle-accurate DRAM models are prevalent in today's computer architecture simulations. However, cycle-accurate models by design are time consuming and not scalable. In this paper, we present a statistical approach of DRAM latency modeling. Unlike previous works, our approach converts DRAM latency modeling into a classification problem and employ machine learning models such as decision tree and random forest to solve the classification problem. We propose 4 basic DRAM latency classes to simplify and parameterize the classification, and extract features that help classification from memory request streams on the fly. We use synthetic traces to train the statistical model and test the model on real-world benchmarks in both accuracy and speed against a cycle-accurate simulator. The results show our statistical models improves the DRAM simulations speed by up to 400 times with 98% average classification accuracy for all the benchmarks we have tested.