Circuit proposition for realization of approximated fractional order systems

This paper gives an effective alternative approach for circuit realization of a block containing a real zero and a pair of complex conjugate poles. The proposed approach is useful for analog realization of a class of integer order systems as well as fractional order systems (FOS) via integer order approximation. The proposed approach makes the system less sensitive to noise while the number of components used is a minimum. The method has been demonstrated by three examples of FOS via their integer approximation. Fractional order transfer functions have been approximated over a frequency range of (0.01-1000) rad/sec, and in all the three cases, the pair of complex conjugate poles and one of the real zeros of approximants have been realized through PSPICE simulation. For one example, the circuit has been implemented in hardware also. Experimental results are compared with PSPICE simulation results and theoretical results.