A low noise, radiation tolerant CCD readout processor for the proposed SNAP satellite.

To simplify the system integration, thermal design and wiring of the SNAP satellite focal plane a custom IC has been developed that can digitize the four output channels of a CCD. This CCD readout IC is designed to operate at room temperature for test purposes and at 140 K, the operating temperature of the focal plane. The chip consists of four-channels of pre-amplifier, double correlated sampler and 14-bit pipeline AD converter. The chip incorporates an innovative circuitry that selects one of three gain levels on a per-pixel basis to achieve greater than 16-bit dynamic range. It has an on-chip voltage reference and programmable configuration registers. We have tested the performance both at room temperature and at 140 K, as well as the radiation tolerance. The ASIC, implemented in a standard 0.25 mum CMOS technology, has a measured readout noise of 6.2 muV rms at 100 kHz readout speed, a measured non-linearity of plusmn5 LSB and a power consumption of 121 mW.