Quantitative Analysis of High-Pressure Deuterium Annealing Effects on Vertically Stacked Gate-All-Around SONOS Memory

High-pressure (HP) deuterium (D2) annealing was applied to a gate-all-around (GAA) MOSFET to improve device reliability and memory performance. The structure had gate dielectrics of oxide–nitride–oxide (ONO), which completely straddled vertically stacked multiple silicon nanowires (Si-NWs) with n+ poly-Si gates. The HP D2 annealing was effective for the vertically stacked GAA MOSFET as it was for a conventional planar MOSFET. In addition, the resistance of the n+ poly-Si gate was also reduced after the HP D2 annealing. This is attributed to the passivation of defects among adjacent poly-Si grains by the HP D2. The reduced gate resistance ( ${R}_{G}$ ) is advantageous for decreasing RC delay. Direct characterizations of dc ${I}$ – ${V}$ and analyses of ac low-frequency noise (LFN) supported the abovementioned behaviors.