A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference

Sub-sampling phase detectors (SSPDs) have recently been demonstrated to enable phase-locked loop (PLL) realizations with very low in-band noise. However, the PLL becomes susceptible to disturbances or interference via substrate or power supply coupling as experienced in systems on chip (SOCs), which could put the PLL out of lock. A tri-state phase-frequency detector with a dead-zone is traditionally added to act as an auxiliary frequency-locked loop (FLL) to enable the PLL to regain lock, albeit after a long delay. We propose a different solution to combine a tri-state PFD with an SSPD wherein the PLL is prevented from losing its lock while simultaneously achieving an improved in-band phase noise performance. A 2.2 GHz integer-N PLL has been prototyped in a 65 nm CMOS process to demonstrate the advantages of the proposed combined phase detector. It was experimentally verified that the PLL is more robust to disturbances than a PLL with a sub-sampling phase detector; it achieves a measured in-band phase noise of $-$ 122 dBc/Hz when operating with the proposed combined PD from a 1.1 V supply voltage.