BGA Package for DDR3 Interface – 4 vs 6 Layers Design Strategy and Electrical Performance Comparison

In the most advanced automotive applications, where high frequency signals, design density, high pin-count, miniaturization and integration dominate the scene, the use of Ball Grid Array (BGA) package is necessary to guarantee an excellent performance of devices. This is possible thanks to the higher design flexibility and the compatibility with advanced interconnection technologies like Flip Chip (FC), that allow shorter overall connections inside IC–Package systems. In this context, the trade-off between performance and production costs must be deeply analyzed, in order to drive the choice of materials and technologies to be used for substrates, which represent a significant cost factor in laminate-based packages. This work describes the comparative analysis between a 4-layer and a 6-layer stack-up on a BGA package designed for the same Double Data Rate 3 (DDR3) high speed interface for automotive application. The applied technology combines Flip Chip Solder Bump (FCSB) and High Density Interconnect (HDI) substrate, that uses blind and buried vias. The comparison involves multiple aspects, starting from pre-layout analysis, to the different strategies used during the design implementation, to the Signal Integrity (SI) and Power Integrity (PI) electrical performance. In this field of applications, packages with at least 4-layer substrates are recommended in order to use an optimized microstrip signal-routing with a solid ground reference and dedicate one metal layer to the different power domains. This design strategy helps both SI and PI efficiency. However, 6-layer substrates, despite the additional cost, give a further improvement: for high density signal-routing, the higher flexibility in terms of layers assignment allows an efficient stripline configuration. This leads to enhanced SI parameters (Insertion and Reflection Losses, Crosstalk), while keeping similar advantages in terms of PI. In this analysis, it will also be shown, for both substrates, how Power Integrity can be improved by using Surface Mounting Technology (SMT) decoupling capacitors. The results of SI and PI that will be discussed are obtained by electrical simulations: this permits to quantify the differences between the design strategies considering the operating frequencies of the DDR3 interface.