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Acemap > Paper > 考慮電源完整性與輸出/入埠限制之積體電路設計配置方法; VLSI Design Planning with Power Integrity and I/O Constraints

考慮電源完整性與輸出/入埠限制之積體電路設計配置方法; VLSI Design Planning with Power Integrity and I/O Constraints

2010 
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