A Low Temperature Process (⩽600°C) of Unhydrogenated In-Situ Doped Polysilicon Thin Film Transistors for Active-Matrix Applications

Low temperature unhydrogenated in-situ doped polysilicon thin film transistors with a SiO 2 deposited gate insulator are elaborated through a four-mask aluminium process. The two polysilicon layers, which constitute active layer and in-situ doped source and drain regions, are deposited at a pressure (P = 90 Pα) in the amorphous state and crystallized by a thermal annealing. This last one is performed before plasma etching of the source/drain polysilicon layer. An oxygen plasma + RCA-type wet cleaning are ensured to obtairn a good APCVD SiO 2 gate insulator/active layer interface quality. These thin film transistors exhibit very high electrical properties: a low threshold voltage (≈ 2 V), a high field effect mobility (≫ 60 cm2/ Vs), and a high On/Off state current ratio (⩾ 107) for a drain voltage V ds = 1 V.