Designing of Charge Pump for Fast-Locking and Low-Power PLL

 Abstract— The specific property of fast locking of PLL is required in many clock and data recovery circuits. Many researchers (1), (3), (5) have tried to reduce this locking time but at the expense of power, phase noise and jitter. This paper presented a PLL with redesigning of individual blocks like- PFD is designed using edge triggered D flip flop to reduce area and static phase error, CP is designed using current mirrored structure to minimize the current mismatch with increased output voltage and VCO has been designed using self bias differential ring oscillator to achieve low jitter operation of PLL. The PLL is designed using 180 nm CMOS technology for high performance with 1.0 V power supply.