Clock skew tolerant communication scheme for SoC IP blocks

System-on-chip (SoC) designs have different intellectual property (IP) blocks that operate on independent clocks and signals crossing the clock domains could experience errors. This paper details the effects of clock skew on data and clock signals at the interface logic of communicating SoC modules. The clocks under consideration have the same frequency but with phase angles that range from 0 - 360deg. A single buffer between communicating modules shows data transfer rates of 10.25 times 10 9 data samples per second serially when the sender and receiver clocks have no skew. Increasing the phase shift (skew) between the sender and receiver clocks degrades this transfer rate to 6.75 times 10 9 samples per second per channel. Adjusting the phase shift between the sender and receiver clocks to always be between 0deg and 135deg improves the performance, keeping the data transfer rates in the range of 9.50 times 10 9 to 10.25 times 10 9 samples per second per channel. It is also shown that the interface logic tolerates skew significantly better if multiple stages of the interface logic and data path FIFO buffers are used.