25 Gbps EML TOSA employing novel impedance-matched FPC design

Toshitsugu Uesugi,Norio Okada,Takeshi Saito,Takeshi Yamatoya,Yoshimichi Morita,Atsushi Sugitatsu

25 Gbps EML TOSA employing novel impedance-matched FPC design

2009

Toshitsugu Uesugi
Norio Okada
Takeshi Saito
Takeshi Yamatoya
Yoshimichi Morita
Atsushi Sugitatsu

25 Gbps EML TOSA employing novel impedance-matched flexible printed circuit design realizes 30 GHz 3-dB bandwidth and a low-jitter optical waveform with 39 % mask margin for 100 Gbps Ethernet applications.

Keywords:

Jitter
Impedance matching
Electronic engineering
Engineering
Electrical impedance
Ethernet
Flexible electronics
Embedded system
Bandwidth (signal processing)
Circuit design
Waveform
Inductance

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