CMOS Analog Matched Filter for DS-CDMA System Based on Operational Amplifier

This paper describes a novel matched filter for CDMA system. The structure of the proposed matched fil- ter mainly consists of two parts: a voltage follower with a sample hold circuit and a selector which changes the pseudo- noise sequence (PN sequence) pattern. From the results of SPICE simulation, it is found that the proposed matched filter operates at the chiprate of 5 MHz and over. In addition, we found that the power consumption of the proposed matched filter is 47.3 mW at 5 V power supply. The proposed matched filter has been realized in a 1.2 "m CMOS process.