Robust and Low Cost TSV Backside Reveal for 2.5D Multi-Die Integration

TSV backside reveal is one of the key process modules for enabling 2.5D integration. This paper presents a robust and low cost solution for TSV backside reveal. 300mm wafers with a TSV size of 10µm×100µm are used to evaluate the proposed backside reveal solution. A high selective wet etching process with an etch rate of about 15 µm/min is used to replace conventional Si dry etching step for Si recess etch. A low temperature cured polyimide layer is used for the backside passivation and an innovative exposure treatment is employed to expose the back tip of the TSVs. After silicon oxide dry etching, the TSV metal is revealed for backside interconnection. This process can avoid Si dry etching, plasma deposition and chemical mechanical polishing (CMP) processes and hence the overall cost is significantly reduced. Furthermore, the process margin for TTV control is also relaxed, which leads to a robust process result. Electrical test results for TSV kelvin and TSV daisy chain show a high process yield and a low contact resistance between the TSV back tip and backside RDL layer. Finally, 2.5D multi-die integration is demonstrated based on the proposed process.