Increased integrity of the metal gate stacks with large ε by preserving a resist material on end portions of gate electrode structures

A method comprising: Preparing a test device having Forming a gate layer stack of a semiconductor device over a first active region, a second active region and an isolation region which separates the first and the second active region along widthwise direction from one another laterally, wherein the gate layer stack comprises a dielectric material having a large e; Forming a first gate electrode structure and a second gate electrode structure from the gate layer stack, wherein the first and the second gate electrode structure are laterally aligned along the width direction and are separated by the isolation region by a lateral distance corresponding to the design rules; Forming a spacer layer propriety; Forming an initial resist mask so that it covers the second active region and the second gate electrode structure selectively, wherein the initial resist mask has a pronounced Lackfus in the lower area, which markedly further processing of the test device during the patterning of the spacer layer and in the production of recesses in the would affect the first active region; and Executing a Lacktestatzprozesses on the test device based on a predefined etch recipe such that coating material is removed at least at a foot of the resist mask, to provide a reduced resist mask; Determining a degree of material erosion when running the Lacktestatzprozesses on the basis of predefined etch recipe and the lateral distance; Forming a semiconductor device having the same transistor design form as in the test device with a modified resist mask, wherein a lateral overlap of the modified resist mask is adjusted using the determined degree of erosion material such that is avoided in exposing an end portion of the second gate electrode structure over the isolation region during the Lackatzprozesses on the basis of predefined etch recipe.