High voltage I/O FinFET device optimization for 16nm system-on-a-chip (SoC) technology

High voltage I/O FinFET device optimization for a 16nm system-on-a-chip (SoC) technology is presented. After careful optimization through high electric field (E-field) mitigation by junction engineering, I/O FinFET devices with leakage current reduction by 1∼2 orders, hot carrier injection (HCI) lifetime improvement by 2.8×/1.2× for N- and PMOS, respectively, and junction breakdown voltage (V bd ) improvement by more than 0.8V are achieved.