Parametric Inspection of 6T SRAM Cell

Due to the rapid advancements in the field of low power circuits and fabrication technology, the responsible factor which affects the circuit's consistency is gaining importance day by day. Static_Random_Access_Memory (SRAM) is amongst the most important circuit used in low-power VLSI systems. Static_Noise_Margin (SNM), Read margin (SNM_R) and Write margin (SNM_W) are the some of the primary performance parameter along with power and delay of the SRAM_Cell. Various factors affect the SNM_R and SNM_W of the SRAM cell. The main objective of this work is to deal with the effect of Pull-up ratio (PR) and Cell_ratio (CR) on the SNM, SNM_R and SNM_W on the 6T SRAM cell along with the effect of supply voltage on the SNM, SNM_R and SNM_W. The effect of $V_{dd}$ , PR and CR on average power and delay is also mentioned in this paper. We have chosen 6T SRAM cell because it is most widly used and very compact due to its symmetry and require very less area. The circuit is being simulated in the Industry standard Cadence (Virtuoso) environment by using 180nm Generic Processes Design Kit.