NMOS multiplexer for fiber optics

The design, layout, and testing of a 5 Mb/s digital multiplexer using 2-/spl mu/m design rules for fiber-optic applications are described. Using a common 10-bit bus, the chip reads data from 16 sources in response to a DATA READY signal. Serial output includes a parity bit and is sent to an LED driver. Handshaking, sequential control, parity checking, and data formatting are covered.