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A Low-Power DSP Core Architecture for Low Bitrate Speech Codec(Special Section on Digital Signal Processing)
A Low-Power DSP Core Architecture for Low Bitrate Speech Codec(Special Section on Digital Signal Processing)
1998
Hiroyuki Okuhata
Morgan Hirosuke Miki
Takao Onoye
Isao Shirakawa
Keywords:
Speech recognition
Mathematics
Codec2
G.723.1
Speech coding
Codec
Real-time computing
Digital signal processing
Enhanced Variable Rate Codec
Architecture
Adaptive Multi-Rate audio codec
Theoretical computer science
Very-large-scale integration
Computer hardware
Correction
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