A Fast Yield Estimation Approach Considering Foundry Variation for Analog Design

Herein, we propose a fast yield estimation approach for analog circuits design in which we combine the behavioral model of circuit and the Quasi-Monte Carlo (QMC) sampling technique to accelerate yield estimation process. The behavioral model is constructed in Verilog-A based on the simulation results which are done at transistor-level; then, the accuracy of the model is verified by experimental testing on a specific analog circuit. Furthermore, instead of using random circuit samples, in this work, QMC circuit samples are adopted to obtain faster convergence rates for the yield prediction process. In conventional analog design stage, designers repeat a number of yield estimation process to select the optimal design point. Each yield estimation effort is a time-consuming process since designers have to simulate on a large number of circuits. Unlike the conventional method, in this work, we build a look-up table for constructing behavioral model of any given circuit; then, this table can be reused in repeating the yield-estimation processes. Therefore, the proposed method can significantly reduce the time for the yield estimation process. Experimental results show that the proposed approach can speed-up the yield estimation process 8 times compared to conventional simulation-based methods with a reasonable drop in accuracy (less than 5%).