Pipeline Design for Quasi-Orthogonal Dsp's

We have observed in current single-chip DSP's the same pipeline design problem which occurs in Long Instruction Word processors. The problem is simplified by the shorter microinstruction, but is complicated by the assumed off-chip peripherals. One is forced to deal with these external sources of non-orthogonality. Based on a multi-layered representation of pipeline entities, each with a definite flow role, we substitute an obscure 'virtual pipeline invisibility' by a neat 'quasi-orthogonality': one should abstract the actual processor into those entities, pushing non-orthogonality to the lowest possible layer of the representation. The abstraction gives the application designer an explicit view of the available resources and their limitations, As shown for a concrete example, viz. off-chip memory extensions, one is provided with the necessary pieces of information to achieve pipeline efficiency.