Proactive Supply Noise Mitigation and Design Methodology for Robust VLSI Power Distribution

To robustly provide the low-noise supply voltage through a VLSI power distribution network (PDN) system, we have proposed a proactive noise mitigation system and improved the low-noise PDN design methodology. For the proactive noise mitigation, we present a lightweight current prediction solution, which predicts the near future noise, and a major-minor voltage regulator (MMVR) structure to provide the fast and wide-range voltage scaling capability. For the low-noise PDN design methodology, we introduce a chip load model to fill the gap between off-chip PDN design and on-chip timing information.