An Overview of ISA Design

This chapter covers some of the main issues the designer of an instruction set for an embedded processor (in particular for a VLIW processor) faces. One of the underlying principles that should guide any architecture design is: Make the compiler's life easy. The catch is that from a pure hardware design point of view it is often easy to design simple features that have very negative repercussions on the compiler. These designs are driven by the promise of saving a few gates or some code. Unfortunately, these seemingly innocuous features sometimes force compilers to behave much more conservatively, hurting performance across the board. This tension between hardware and compiler mentalities has been a constant factor in the majority of ISA designs, and finding the right balance is one of the most critical tasks for a processor architect. The chapter considers several factors in the design of an ISA—including expressiveness and regularity of the instruction set, cost, relationship to the compiler, and design styles—for some of the most widely adopted choices. Readers who are familiar with RISC processors will find many similarities, as should be expected, given the close ties between RISC and VLIW. In deciding the areas to explore, the chapter chooses to cover more extensively what is more relevant to a modern embedded VLIW.