Comparitive analysis of power optimization using mtcmos, transistor sizing & combined technique on 180nm technology

This is a review paper in which we use various techniques for low power optimization and with the help of these techniques we perform comparative analysis. Evolution in VLSI continuously reduce the silicon technology to fulfill the increasing demands for higher functionality, low power and better performance at low cost. In today’s scenario, low power design becomes an important issue. Most of the power consumption takes place during switching events i.e. dynamic power. This paper present various basic circuit in which reduction in power consumption takes place due to transistor sizing as well as MTCMOS technique separately and then we will also design the same circuit by the combination of the above two techniques which consume overall less power than conventional CMOS circuitry. Basic circuit are fundamental components of any digital design. We also see the effect of voltage scaling on these circuit and reduce the circuit using shannon’s expansion theorem without changing in functionality ,to reduce the transistor count so that power decrease. The investigation has been carried out with simulation run environment on cadence virtuoso design editor using 180nm CMOS process technology at 1.8 V.