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Gate first high-k/metal gate stacks with zero SiOx interface achieving EOT=0.59nm for 16nm application
Gate first high-k/metal gate stacks with zero SiOx interface achieving EOT=0.59nm for 16nm application
2009
Huang
HeH.
Sivasubramani
Kirsch
Bersuker
Gilmer
Quevedo López
Hussain
Majhi
Lysaght
Park
Goel
Young
Cruz
Diaz
Hung
Price
Tseng
Jammy
Keywords:
Dielectric
Silicon
High-κ dielectric
International Electron Devices Meeting
Annealing (metallurgy)
Logic gate
Materials science
Transistor
Optoelectronics
Bismuth
Correction
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