On-chip mixed-signal test structures re-used for board test

Analogue clusters on boards are traditionally tested in mass production using a Bed-of-Nails, often combined with functional system tests. In general this approach requires additional board area to create test access, is not very flexible and is hard to re-use. On-chip methods provide a solution to overcome these drawbacks and are already widely used in the form of boundary scan for digital interconnections. For analogue interconnections also on-chip solutions are available. We analysed the coverage and application of two on-chip methods, IEEE Std 1149.4 and the re-usage of existing design-for-testability for on-chip mixed-signal blocks. It was found that a reduction board test costs as well as test development time can be achieved by using, or rather reusing on-chip alternatives.