Hybrid dual-mode low voltage dropout regulator with infinite impulse response digital filters

In this paper we will demonstrate the implementation of a low-dropout hybrid regulator (LDO) that includes a continuous to discrete time feedback loop, in a 28 nm TSMC CMOS technology. The proposed LDO will be given an apriori signal to differentiate between low and high load current states. This mixed mode design is scalable ensuring the best regulation at different load currents for dual or multichannel LDO designs. It has a maximum overshoot of less than 5 mV and undershoot of less than 50 mV with steady state ripple of less than 5 mV. The maximum switching transient time to steady state regulation was found by simulation to be under 830 ps.