A Fault Check Graph Approach for Photonic Router in Network on Chip

Photonic Network-on-Chip (PNoC) has been a new trend for next generation multi-processor system. However, components, such as Micro-Ring Resonators (MRRs), in PNoC are fault prone and would not provide reliable operation unless fault components in the routers are detected and masked properly. There is very little work done to analyze and detect fault in PNoC. An approach based on fault check graph is proposed. An n-port photonic router is modelled as a complete weighted directed graph, which is called pre-Fault Check Graph, and MRR model is created. By the complete weighted directed graph and fault simulation, the proposed method is established with fault check graph and MRR model. The experimental results prove that the proposed approach is effective with corresponding fault simulation.