Digital background calibration of ultra-high-speed time-interleaved of PAM4 2-bit DACs

Abstract Sample-time error (STE) between time-interleaved channels is one of the main limitations on the performance of time-interleaved digital to analog converters (DACs). This paper presents techniques for detecting and correcting the STE in ultra-high speed 53 GBaud 4-level pulse amplitude modulation (PAM4) with a 2-Bit DAC. Simulation results and lab measurements of a TSMC 16nm CMOS process are presented. Test results show that the peak-to-peak STE of the 53 GBaud DAC is improved by more than one order of magnitude.