Analysis of Triple-Threshold Technique for Power Optimization in SRAM Bit-Cell for Low-Power Applications at 45 Nm CMOS Technology

As the technology node is shrinking from micron to sub-micron and to deep sub-micron, the device size of semiconductor components is getting smaller and smaller to achieve greater functionality. It has been established that the power consumption in the technology >100 nm is largely dominated by the active power dissipation. The technology <100 nm (more transistors on a single chip area), the active power dissipation is no longer a power dominant component as compared to static power dissipation. At the lower CMOS technology nodes, the threshold voltage of the devices also decreases. Therefore, the devices have become more noise sensitive (bit-cell) which affects the stability of the systems profoundly and degrade the overall system performance. The threshold voltage reduction also challenges the device sub-threshold leakage current and noise margin. To address this issue, this work presents the triple-Vth CMOS transistors approach which have different threshold voltages. It is found that the read/write data stability is improved by 10% at the cost of area overhead of one transistor.