A highly robust SiGe source drain technology realized by disposable sidewall spacer (DSW) for 65nm node and beyond

A SiGe source drain (SD) technology by using a disposable sidewall spacer (DSW) for high performance PMOSFET is proposed to avoid device degradation induced by high temperature epitaxial process. DSW process is effective for suppressing gate depletion and short channel effect (SCE). A successful integration of DSW process into SiGe SD PMOSFET is performed to generate strain in the channel region, enhancing hole mobility. Characteristics examined include SCE as well as drivability of SiGe SD PMOSFET. It is found that drive current enhancement is strongly affected by the parasitic resistance as well as the strain effect. 35% enhancement in saturation drive current is achieved by optimizing both the strain effect and the parasitic resistance, while threshold voltage roll-off characteristic is the same as a reference device which is fabricated by conventional bulk process.