A 1.4GS/s 9-bit 45 dB power control RFDAC for digital radio transmitters

This paper presents a high speed, 9-bit RF Digital-to-Analog Converter based on a new architecture implemented in a 0.13 μm BiCMOS process and able to adjust the output power by 45 dB to meet gain control requirements of the new communications standards with a SFDR >25 dBc. The maximum test-demonstrated frequency is 1.4 GHz and the chip dissipates <25 mW.