Test Compaction of Logic Blocks by using Fault Identification Method

An arbitrary design implemented into a field-programmable gate array (FPGA). FPGA contains many logical blocks. Fault equivalence and fault dominance method are used to detect the fault with minimum time period. An approach provides transparent scan to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. The transparent-scan sequences based on tests for one logic block could detect faults in other logic blocks, with different numbers of state variable. It uses n number of test configuration instead of 2 n number of test configuration by test code algorithm. Transparent scan enhances the ability to produce a compact test set for a group of logic blocks. The procedure obtains a set of transparent-scan sequences for a group of logic blocks from compacted test sets for the logic blocks in the group. From this set, it chooses a subset that finds all the target faults, which are propagated by the complete set by using Modelsim and area is obtained by using the XILINX ISE 8.1 software. An approach to test application called transparent scan, the scan-select and scan-chain inputs of a scan circuit are considered as inputs of the sequential circuit in the same way as the primary inputs, and the scan-chain outputs are considered as outputs in the same way as the primary outputs. A test sequence under transparent scan specifies the values for all the inputs without distinguishing between them based on the types. The corresponding output sequence specifies values for all the outputs, again, without distinguishing between them based on their types. Faults are allowed to be detected during all the clock cycles of a transparent-scan sequence. In general, fault coverage is computed by sequential fault simulation of the transparent-scan sequence. This view of the test