Design of pipelined mixed-signal fuzzy logic controller with linguistic hedge modifiers

In this paper, we realize the linguistic hedge fuzzy logic controller in a mixed-signal VLSI design with pipelined clocking strategy. Current-mode approach is adopted in designing the signal processing portions to simplify the circuit complexity; digital circuits are adopted to implement the programmable units. All the designs are performed with HSPICE simulation in level 28 model for a 0.35 /spl mu/m SPQM CMOS process. The pipelined strategy speeds up the inference operation to 0.5 M FLIPS. The supply voltage of this system is 3.3V.